In the current technology of integrated circuits, the dimensions of the devices in the integrated circuits are smaller than one-micron meters. In the manufacture of ultra large-scale integrated (ULSI) circuits, the channel's length of transistors is below 0.5 micron meters. The short channel effect often arises in the manufacture of the ULSI circuit. One approach of reducing the short channel effect is a self-aligned silicide (Salicide) of the active region in a transistor. The salicide process can reduce the contact resistance of the ULSI devices and improve the operation speed of the devices. In IEDM Tech. Dig. in the page 73 on 1996, P. Fornara et al. described the application of the salicide process to the short-channel transistors. In this paper, the authors discussed the formation of TiSi.sub.2 or CoSi.sub.2 on spacers and produced simulating structures of metal films on the spacers. The well-known salicide process is now one of the most efficient ways of obtaining self-aligned low resistive contacts in CMOS and BiCMOS technology. The silicide layers are not formed on spacers of devices and has different topographical results which depend on the materials of the silicide layers.
Salicide processes are used to reduce the contact resistance of the ULSI MOS devices but the devices show worse electrostatic-shielding-devices (ESD) performance than the nob-salicide devices. On page 893 of IEDM Tech. Dig. on 1996, A. Amerasekera et al. discussed the relationship between the salicide thickness on devices and the current gain of the devices. In this paper, the authors concluded that the thicker salicide of the device could degrade the ESD performance of the device and found a phenomena that junction depths and salicide thickness in a 0.25 micron meters CMOS process affect the current gain of a self-biased lateral NPN transistor. The relationship between the current gain and the ESD performance is discussed in this paper. According to this paper, the salicide process can prevent the short-channel effect of the ULSI MOS devices but can degrade the ESD performance of the devices. Devices with lower current gain are found to have lower ESD performance. Current gain is observed to be strongly influenced by the effective drain/source diffusion depth below the silicide which is determined by the implant energy as well as the amount of active diffusion consumed in silicidation.
Therefore, using the salicide process to manufacture the ULSI devices but not influence the ESD performance of the devices is an important topic.